The present invention relates in general to the testing of optoelectronic components in integrated circuits (ICs) that utilize v-grooves to couple input/output (IO) photonic signals between optical fibers and the IC. More specifically, the present invention relates to fabrication methodologies and resulting structures that allow the efficient and cost-effective testing of optoelectronic components in ICs prior to v-groove formation and coupling.
Semiconductor devices are used in many electronic and other applications. ICs are typically formed from various circuit configurations of semiconductor devices formed on semiconductor wafers. Alternatively, semiconductor devices can be formed as monolithic devices, e.g., discrete devices. Semiconductor devices are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, patterning the thin films of material, doping selective regions of the semiconductor wafers, etc. In a conventional semiconductor fabrication process, a large number of semiconductor devices are fabricated in a single wafer. After completion of device level and interconnect level fabrication processes, the semiconductor devices on the wafer are separated and the final products is packaged. CMOS (complementary metal-oxide semiconductor) is the semiconductor fabrication technology used in the transistors that are manufactured into most of today's computer microchips. In CMOS technology, both n-type and p-type transistors are used in a complementary way to form a current gate that forms an effective means of electrical control. Processing steps performed later in CMOS technology are referred to as back-end-of-line (BEOL) CMOS processing, and processing steps performed earlier in CMOS technology are referred to as front-end-of-line (FEOL) CMOS processing.
Interconnect bottlenecks are mitigated, and in many cases overcome, by replacing selected IO electrical signals and metallic connections on ICs with optical signals and optical couplers. The optical IO signals, once coupled from optical fibers to the IC, are routed to target downstream optoelectronic components, as well as output optical fibers. ICs often use v-grooves for edge-coupling to optical fibers in the final packaged product. However, the optical access required for testing ICs that use v-groove coupling is only available after v-groove etching, dicing and packaging, which are expensive and time-consuming BEOL processes. Accordingly, the testing of v-groove coupled ICs is often performed on separate test ICs having inputs and outputs connected using optical couplers that do not require expensive and time-consuming fabrication. Such testing approaches and configurations provide some information but do not allow testing of the actual IC product.
It is therefore desirable to test the performance of actual v-groove coupled IC products at the wafer-level before v-groove etching, dicing and packaging in order to acquire statistical yield and performance data and package only known-good dies.